Embedded-system architecture is the structural organization of processor, memory, input-output peripherals, buses, communication interfaces and software components used to implement a dedicated system.
An architecture defines how instructions and data are stored, fetched, processed and transferred between different units of an embedded system.
Basic Architectural Components
+---------------------------+
| Input Devices / Sensors |
+------------+--------------+
|
v
+---------------------------+
| Processor / Controller |
| ALU | CU | Registers |
+-----+----------+----------+
| |
v v
+----------+ +----------------+
| Memory | | I/O Peripherals|
| ROM/RAM | | Timer, ADC, PWM|
+----------+ +----------------+
|
v
+---------------------------+
| Output Devices / Actuator |
+---------------------------+
Main Functions
Instruction fetching and execution
Data storage and transfer
Peripheral control
Real-time response
Communication with external devices
2. Von Neumann Architecture 14 Marks
Von Neumann architecture uses a common memory and a common bus for both program instructions and data.
+------------------+
| CPU |
| ALU + CU + Reg. |
+--------+---------+
|
Common Address,
Data and Control Bus
|
+--------+---------+
| Common Memory |
| Program + Data |
+------------------+
Working
The processor places an instruction address on the address bus.
The instruction is fetched from the common memory.
The processor decodes and executes the instruction.
If data is required, the same bus and memory are used again.
Instruction fetch and data transfer generally occur one after another.
Advantages
Simple architecture
Lower hardware cost
Flexible allocation of memory
Easy system design
Limitations
Instruction and data cannot normally be fetched simultaneously.
Common bus becomes a performance bottleneck.
Program and data share the same memory bandwidth.
The limitation caused by one common path for instructions and data is called the Von Neumann bottleneck.
3. Harvard Architecture 14 Marks
Harvard architecture uses separate memories and separate buses for program instructions and data.
+-------------------+
| Instruction Memory|
+---------+---------+
|
Instruction Bus
|
+-----v------+
| CPU |
| ALU/CU/Reg |
+-----+------+
|
Data Bus
|
+---------v---------+
| Data Memory |
+-------------------+
Working
The CPU fetches an instruction through the instruction bus.
At the same time, data can be read or written through the data bus.
Separate memories may use different widths and technologies.
Parallel transfer improves execution speed.
Advantages
Simultaneous instruction and data access
Higher memory bandwidth
Faster execution
Separate protection of program and data
Different memory sizes and word widths are possible
Limitations
More complex hardware
Higher implementation cost
Fixed separation may reduce memory flexibility
Many microcontrollers and digital signal processors use Harvard or modified Harvard architecture.
4. Von Neumann vs Harvard Architecture 14 Marks
Feature
Von Neumann
Harvard
Memory
Common program and data memory
Separate program and data memory
Buses
Single shared bus
Separate instruction and data buses
Speed
Comparatively lower
Comparatively higher
Simultaneous access
Normally not possible
Possible
Complexity
Simple
More complex
Cost
Lower
Higher
Memory flexibility
High
Limited by separate memories
Common use
General computers
Microcontrollers and DSPs
5. Instruction Set Architecture 14 Marks
Instruction Set Architecture, or ISA, is the interface between processor hardware and software. It defines the instructions, registers, data types, addressing modes and memory model visible to a programmer.
Elements of ISA
Instruction formats
Operation codes
Processor registers
Supported data types
Addressing modes
Memory addressing
Interrupt and exception mechanism
Input-output model
Instruction Categories
Data transfer instructions
Arithmetic instructions
Logical instructions
Branch and control instructions
Bit-manipulation instructions
Input-output instructions
Common Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Indexed addressing
Relative addressing
ISA specifies what the processor can do, while microarchitecture describes how the processor internally implements that ISA.
6. CISC Architecture 14 Marks
CISC stands for Complex Instruction Set Computer. It uses a large set of powerful instructions, where a single instruction may perform several low-level operations.
Characteristics
Large instruction set
Many addressing modes
Variable-length instructions
Complex instruction decoding
Memory-to-memory operations may be supported
Microprogrammed control is common
Fewer instructions may be needed for one program
Advantages
Compact machine code
Powerful instructions
Fewer instructions for complex operations
Good support for high-level language constructs
Limitations
Complex processor design
Higher power consumption
Instructions may require multiple clock cycles
Pipelining is comparatively difficult
Examples
8051 microcontroller
x86 family
Motorola 68000 family
7. RISC Architecture 14 Marks
RISC stands for Reduced Instruction Set Computer. It uses a smaller set of simple instructions designed for fast and efficient execution.
Characteristics
Small and simple instruction set
Fixed-length instructions
Few addressing modes
Load-store architecture
Large number of general-purpose registers
Most instructions execute quickly
Efficient pipelining
Hardwired control is commonly used
Advantages
Simple processor design
High execution speed
Efficient instruction pipeline
Lower power consumption
Suitable for embedded and mobile systems
Limitations
A task may require more instructions.
Program size may increase.
Compiler quality is important.
Examples
ARM
MIPS
SPARC
RISC-V
8. CISC vs RISC 14 Marks
Basis
CISC
RISC
Instruction set
Large and complex
Small and simple
Instruction length
Variable
Mostly fixed
Clock cycles
May require multiple cycles
Often designed for fast execution
Addressing modes
Many
Few
Control unit
Often microprogrammed
Often hardwired
Pipeline
More difficult
More efficient
Registers
Comparatively fewer
Comparatively more
Code size
Usually smaller
May be larger
Example
8051 and x86
ARM and MIPS
Modern processors may combine features of both approaches, so the distinction is not always absolute.
9. Basic Embedded Processor Architecture 14 Marks
+-----------------------------------+
| Processor |
| +------+ +------+ +------------+ |
| | ALU | | CU | | Registers | |
| +------+ +------+ +------------+ |
+----------------+------------------+
|
System Bus
+-------------+-------------+
| | |
+--v---+ +---v----+ +---v------+
| ROM | | RAM | | I/O Unit |
+------+ +--------+ +----------+
Major Units
ALU: Performs arithmetic and logical operations.
Control Unit: Fetches, decodes and controls instruction execution.
Registers: Store operands, addresses and intermediate results.
Program Counter: Holds the address of the next instruction.
Instruction Register: Holds the current instruction.
Stack Pointer: Points to the top of the stack.
Bus Interface: Transfers addresses, data and control signals.
Fetch-Decode-Execute Cycle
Fetch instruction from memory.
Increment or update program counter.
Decode the operation.
Fetch required operands.
Execute the instruction.
Store the result.
10. Microcontroller Architecture 14 Marks
A microcontroller is a single integrated circuit containing a processor core, memory and peripheral devices for embedded control applications.
ARM is a family of energy-efficient RISC processor architectures widely used in embedded, mobile, automotive and IoT systems.
Main Characteristics
RISC-based instruction set
Load-store architecture
Large register set
Efficient pipelining
Low power consumption
High code density through compact instruction support
Fast interrupt handling
Scalable from microcontrollers to application processors
+--------------------------------+
| ARM Processor Core |
| +----------+ +--------------+ |
| | Register | | Instruction | |
| | Bank | | Decoder | |
| +----------+ +--------------+ |
| +----------+ +--------------+ |
| | ALU | | Barrel | |
| | | | Shifter | |
| +----------+ +--------------+ |
| Pipeline and Bus Unit |
+--------------------------------+
ARM Pipeline Concept
Fetch
Decode
Execute
Different ARM implementations may use deeper pipelines, but the basic goal is overlapping instruction stages to improve throughput.
Applications
Smartphones
IoT devices
Automotive controllers
Medical systems
Networking equipment
Industrial automation
Advantages
Excellent performance per watt
Large software ecosystem
Wide range of processor cores
Suitable for battery-powered products
15. DSP Processor Architecture 14 Marks
A Digital Signal Processor is a specialized processor optimized for fast mathematical operations on digital signals such as audio, video, images and sensor data.
Main Features
Fast multiply-accumulate operation
Harvard or modified Harvard architecture
Multiple memory accesses in one cycle
Special addressing modes
Efficient loops
Pipelined execution
Saturation and fixed-point arithmetic support
Digital Input
|
v
+----------+ +------------------+
| ADC |-->| DSP Processor |
+----------+ | MAC, ALU, Memory |
+--------+---------+
|
v
+----------+
| DAC / |
| Output |
+----------+
Multiply-Accumulate Operation
Result = Result + (Input × Coefficient)
This operation is repeatedly used in digital filters, transforms and signal-processing algorithms.
Applications
Audio processing
Speech recognition
Image processing
Radar and sonar
Communication systems
Motor control
Medical signal processing
16. 8051 vs ARM vs DSP 14 Marks
Feature
8051
ARM
DSP
Architecture
CISC microcontroller
RISC processor family
Signal-processing optimized
Typical data width
8-bit classical architecture
Commonly 32-bit or 64-bit families
Depends on DSP family
Main focus
Simple control
General embedded processing
Fast signal computation
Power efficiency
Good for small control
Very good
Optimized for target workload
Special feature
Bit operations and integrated peripherals
Efficient pipeline and register set
Fast MAC operation
Application
Basic appliances
Mobile, IoT and automotive
Audio, video and communication
17. Processor Selection Criteria 7 Marks
Required processing speed
Real-time deadlines
Power consumption
Memory requirement
Available peripherals
Communication interfaces
Unit cost
Development tools
Software support
Reliability and operating environment
Future scalability
Use 8051 for basic low-cost control, ARM for flexible and power-efficient modern embedded applications, and DSP when intensive signal-processing operations dominate.
Unit 2 Quick Revision
Von Neumann uses common program and data memory.
Harvard uses separate program and data memories.
ISA defines the interface visible to software.
CISC uses many complex instructions.
RISC uses simple instructions and supports efficient pipelining.
A microcontroller integrates CPU, memory and peripherals.
8051 is a classic 8-bit CISC microcontroller.
ARM is a power-efficient RISC processor architecture.
DSP processors are optimized for multiply-accumulate operations.
Processor selection depends on performance, power, cost and application.
Important RGPV Exam Questions
Long Answer Questions
Explain Von Neumann architecture with a neat diagram.
Explain Harvard architecture and compare it with Von Neumann architecture.
Define instruction-set architecture and explain its elements.
Explain CISC architecture with advantages and limitations.
Explain RISC architecture with advantages and limitations.
Differentiate CISC and RISC architectures.
Draw and explain the basic embedded-processor architecture.
Explain microcontroller architecture with a neat block diagram.
Differentiate a microprocessor and a microcontroller.
Draw and explain the 8051 architecture.
Explain ARM processor architecture and its features.
Explain DSP processor architecture and applications.
Compare 8051, ARM and DSP processors.
Short Answer Questions
What is the Von Neumann bottleneck?
Define Harvard architecture.
What is ISA?
Define CISC.
Define RISC.
What is load-store architecture?
What is a microcontroller?
List four features of 8051.
Why is ARM suitable for embedded systems?
What is a MAC operation in DSP?
Exam Tip: Practice diagrams of Von Neumann, Harvard, microcontroller, 8051, ARM and DSP architecture. Architecture questions score better when buses, memory units and processor blocks are clearly labeled.
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PYQ Analysis
Repeated Unit 2 questions coming soon.
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Frequently Asked Questions
Von Neumann uses one common memory and bus for data and instructions, while Harvard uses separate memories and buses.
RISC is generally easier to pipeline and is designed for efficient execution, but actual speed depends on processor implementation and workload.
The classical 8051 is generally studied as a CISC microcontroller.
ARM provides strong performance, low power consumption, scalable cores and a large software ecosystem.
DSP processors are used for fast repetitive mathematical operations in audio, video, communication and sensor signal processing.