Memory hierarchy arranges memory levels according to speed, capacity and cost.
Memory Level
Speed
Capacity
Cost per Bit
Registers
Highest
Very small
Highest
Cache
Very high
Small
High
Main memory
Medium
Medium
Medium
Flash or storage
Lower
Large
Lower
As we move downward in the memory hierarchy, capacity generally increases and cost per bit decreases, but access time increases.
3. Locality of Reference 7 Marks
Locality of reference means that a program tends to access the same or nearby memory locations repeatedly within a short period.
Types
Temporal locality: Recently used data or instructions are likely to be used again.
Spatial locality: Locations close to a recently accessed address are likely to be accessed.
Sequential locality: Instructions are often executed in sequence.
Cache memory improves performance by exploiting these locality properties.
4. Cache Memory 14 Marks
Cache is a small and fast memory placed between the processor and main memory. It stores frequently used instructions and data to reduce average memory-access time.
+-----------+ +-----------+ +-------------+
| Processor |<--->| Cache |<--->| Main Memory |
+-----------+ +-----------+ +-------------+
Fast Access Miss causes main-memory access
Cache Hit
The required information is found in the cache.
Cache Miss
The required information is not in the cache and must be fetched from main memory.
Hit Ratio = Number of Cache Hits ÷ Total Memory Accesses
Average Access Time = Hit Time + (Miss Rate × Miss Penalty)
Cache Levels
L1 cache: Smallest and fastest, close to the processor.
L2 cache: Larger but slower than L1.
L3 cache: Larger shared cache in some systems.
Advantages
Reduces processor waiting time
Improves execution performance
Reduces main-memory traffic
Limitations
Increases hardware cost
Requires mapping and replacement logic
Cache misses cause delays
May create consistency issues with DMA or multiple processors
5. Cache Mapping Techniques 14 Marks
1. Direct Mapping
Each main-memory block can be placed in only one fixed cache line.
Cache Line = Main Memory Block Number mod Number of Cache Lines
Advantages
Simple and inexpensive
Fast lookup
Limitation
Different memory blocks may compete for the same cache line, causing conflict misses.
2. Fully Associative Mapping
A memory block can be placed in any cache line.
Advantages
Minimum conflict misses
Flexible block placement
Limitations
Complex hardware
Expensive associative search
3. Set-Associative Mapping
The cache is divided into sets. A memory block maps to one set but can be placed in any line of that set.
Set Number = Main Memory Block Number mod Number of Sets
Method
Placement
Complexity
Conflict Miss
Direct
One fixed line
Low
High
Fully associative
Any line
High
Low
Set associative
Any line in one set
Medium
Medium
6. Cache Replacement Policies 7 Marks
When no free cache line is available, a replacement policy selects a block to remove.
LRU: Replaces the least recently used block.
FIFO: Replaces the oldest loaded block.
Random: Selects a block randomly.
LFU: Replaces the least frequently used block.
Replacement policy is mainly required in associative and set-associative caches.
7. Cache Write Policies 7 Marks
Write-Through
Every cache write is also immediately written to main memory.
Simple consistency
More memory traffic
Slower writes
Write-Back
Data is first updated only in cache. Main memory is updated when the modified block is replaced.
Lower memory traffic
Faster repeated writes
Requires a dirty bit and more complex control
Feature
Write-Through
Write-Back
Main-memory update
Immediately
On block replacement
Memory traffic
Higher
Lower
Control complexity
Lower
Higher
Consistency
Easier
Requires management
8. Virtual Memory 14 Marks
Virtual memory is a memory-management technique that provides each program with a large logical address space and maps it to available physical memory.
Program Generates
Virtual Address
|
v
+----------------+
| MMU / Address |
| Translation |
+-------+--------+
|
v
Physical Address
|
v
+----------------+
| Physical Memory|
+----------------+
Advantages
Provides address-space isolation
Supports memory protection
Simplifies program organization
Allows programs larger than physical RAM in general-purpose systems
Supports controlled sharing of memory
Embedded-System Considerations
Small microcontrollers may not use virtual memory.
Complex embedded systems running operating systems often use an MMU.
Hard real-time systems must carefully control unpredictable page faults.
9. Paging 14 Marks
Paging divides virtual memory into fixed-size pages and physical memory into equal-size page frames.
A TLB is a small and fast associative cache that stores recently used virtual-to-physical address translations.
TLB Hit
The translation is found in the TLB, so address conversion is fast.
TLB Miss
The page table must be accessed to obtain the translation.
Advantages
Reduces address-translation time
Reduces page-table memory accesses
Improves virtual-memory performance
13. Page Fault 7 Marks
A page fault occurs when a referenced virtual page is not currently available in physical memory or the requested access is not permitted.
General Page-Fault Handling
The MMU detects an invalid page-table entry.
A fault exception is generated.
The operating system checks whether access is valid.
The page may be loaded into physical memory.
The page table and TLB are updated.
The interrupted instruction is restarted.
Page-fault handling can take an unpredictable amount of time. Therefore, demand paging is often avoided or carefully controlled in hard real-time systems.
14. Direct Memory Access 14 Marks
DMA is a technique in which a DMA controller transfers data directly between an input-output device and memory without requiring the CPU to move every data item.
+-------------+
| Processor |
+------+------+
|
System Bus
+-----------------+----------------+
| |
+-----v------+ +-----v------+
| DMA |<------------------->| Main Memory|
| Controller | +------------+
+-----+------+
|
v
+------------+
| I/O Device |
+------------+
DMA Working
The CPU initializes the DMA controller with source address, destination address, transfer count and direction.
The peripheral requests a DMA transfer.
The DMA controller requests control of the system bus.
The bus arbiter grants control.
DMA transfers data directly between memory and the peripheral.
The transfer count is updated.
After completion, DMA generates an interrupt to the CPU.
DMA Controller Registers
Source-address register
Destination-address register
Transfer-count register
Control and status register
Advantages
Reduces CPU overhead
Improves data-transfer speed
Allows CPU and peripheral work to overlap
Suitable for large blocks of data
Limitations
Requires additional hardware
Competes with CPU for bus access
Can create cache-coherency problems
Control logic is more complex
15. DMA Transfer Modes 14 Marks
1. Burst Mode
The DMA controller takes control of the bus and transfers an entire block before releasing it.
High DMA throughput
CPU may wait for a longer time
2. Cycle Stealing
The DMA controller transfers one data item at a time by temporarily taking bus cycles from the CPU.
CPU is slowed but not stopped for the whole block
Good balance between CPU and DMA access
3. Transparent Mode
DMA transfers data only when the CPU is not using the bus.
Programmed during manufacturing and cannot normally be changed.
PROM
Can be programmed once by the user.
EPROM
Can be erased using ultraviolet light and reprogrammed.
EEPROM
Can be electrically erased and reprogrammed, often at byte or small-block level.
Memory
Programming
Erasing
Typical Use
ROM
Factory programmed
Not normally possible
Fixed firmware
PROM
One time
Not possible
Permanent configuration
EPROM
Reprogrammable
Ultraviolet light
Older development systems
EEPROM
Electrically programmable
Electrical
Settings and calibration data
19. Flash Memory and EEPROM 14 Marks
Flash memory is a non-volatile electrically erasable memory that is generally erased and programmed in blocks.
Flash Memory Features
Non-volatile
High storage density
Block erase operation
Used for firmware and mass storage
Limited program-erase cycles
EEPROM Features
Non-volatile
Electrical erase and write
Suitable for small configuration data
Usually supports finer-grained writes
Feature
Flash
EEPROM
Erase unit
Block or sector
Byte or small unit in many devices
Density
Higher
Lower
Main use
Program firmware and storage
Configuration and calibration
Update style
Large blocks
Small data updates
20. Memory Interfacing 14 Marks
Memory interfacing is the process of connecting memory devices to a processor using address, data and control buses.
+-----------+ Address Bus +----------+
| Processor |------------------------>| Memory |
| |<----------------------->| Device |
| | Data Bus | |
| |------------------------>| |
+-----------+ Control Bus +----------+
|
Read / Write / Enable
Important Signals
Address bus: Selects a memory location.
Data bus: Transfers data.
Read signal: Requests data from memory.
Write signal: Stores data into memory.
Chip select: Activates a particular memory device.
Address Decoding
Address-decoding logic generates a chip-select signal when the processor places an address belonging to a device's assigned address range.
Steps in Memory Read
Processor places address on address bus.
Decoder activates the memory device.
Processor activates read control signal.
Memory places data on data bus.
Processor reads the data.
Steps in Memory Write
Processor places address and data on buses.
Decoder activates the memory device.
Processor activates write signal.
Memory stores the data.
21. Bus Architecture 14 Marks
A bus is a shared group of signal lines used to transfer addresses, data and control information between processor, memory and peripheral devices.
+-----------+
| Processor |
+-----+-----+
|
====== System Bus =======================
| Address Bus | Data Bus | Control Bus |
| | |
+-----v-----+ +-----v-----+ +-----v------+
| Memory | | I/O Device| | DMA |
+-----------+ +-----------+ +------------+
Types of Bus Lines
Address bus: Carries memory or device addresses.
Data bus: Carries actual data.
Control bus: Carries read, write, interrupt, clock and arbitration signals.
Bus Parameters
Bus width
Clock frequency
Bandwidth
Latency
Number of connected devices
Electrical loading
Arbitration method
Theoretical Bus Bandwidth = Transfers per Second × Bytes per Transfer
22. Bus Read and Write Cycles 7 Marks
Read Cycle
Bus master places an address on the address bus.
It activates the read control signal.
The selected slave places data on the data bus.
The master captures the data.
Control signals are deactivated.
Write Cycle
The master places address and data on buses.
It activates the write signal.
The selected slave stores the data.
The transfer completes and signals are released.
23. Bus Arbitration 14 Marks
Bus arbitration is the process of selecting one bus master when multiple devices request control of a shared bus.
CPU Request ----\
DMA Request -----\ +--------------+
Other Master -----+----->| Bus Arbiter |
+------+-------+
|
Bus Grant
|
v
Selected Master
Need for Arbitration
Prevents two masters from driving the bus simultaneously
Ensures orderly data transfer
Supports priorities
Provides fairness between requesting devices
1. Daisy-Chain Arbitration
The grant signal passes serially through devices. The first requesting device in the chain receives the bus.
Simple and low cost
Fixed priority
Devices later in the chain may wait longer
2. Centralized Parallel Arbitration
Each master has separate request and grant lines connected to a central arbiter.
Fast decision
Flexible priority
Requires more wires and centralized hardware
3. Distributed Arbitration
Devices cooperate to select the winning master without one central arbiter.
No single central failure point
Suitable for distributed systems
More complex design
Priority Policies
Fixed priority
Round-robin priority
Dynamic priority
Time-slice based access
24. Synchronous vs Asynchronous Bus 14 Marks
Synchronous Bus
Bus operations are coordinated by a common clock.
Simple timing
High speed for devices with similar timing
Maximum distance and speed are limited by clock timing
Asynchronous Bus
Bus operations are coordinated using handshaking signals instead of a shared clock.
Supports devices with different speeds
More flexible timing
Control logic is more complex
Feature
Synchronous Bus
Asynchronous Bus
Timing
Common clock
Request-acknowledge handshake
Design
Simpler
More complex
Device speeds
Best with similar speeds
Supports different speeds
Transfer time
Fixed clock-based
Variable
25. Important Comparisons 14 Marks
Cache Memory vs Virtual Memory
Feature
Cache Memory
Virtual Memory
Main purpose
Improve access speed
Provide address translation and larger logical space
Hardware
Fast cache memory and controller
MMU, page tables and operating-system support
Storage
Frequently used blocks
Maps virtual pages to physical frames
Miss event
Cache miss
TLB miss or page fault
Real-time impact
Misses add timing variation
Page faults may cause large delays
Program Memory vs Data Memory
Program Memory
Data Memory
Stores executable instructions and constants.
Stores variables, stack and temporary results.
Usually non-volatile Flash or ROM.
Usually volatile SRAM or DRAM.
Often read frequently and written less often.
Read and written frequently during operation.
CPU Transfer vs DMA Transfer
CPU-Controlled Transfer
DMA Transfer
CPU moves every data item.
DMA controller moves data directly.
High CPU overhead.
Low CPU overhead.
Suitable for small transfers.
Suitable for blocks and high-speed I/O.
Unit 4 Quick Revision
Memory hierarchy balances speed, capacity and cost.
Cache stores recently used instructions and data.
A cache hit is faster than a cache miss.
Direct, associative and set-associative are cache mapping methods.
Virtual memory maps logical addresses to physical addresses.
The MMU performs address translation and protection.
A TLB caches recent address translations.
Paging divides memory into pages and frames.
DMA transfers data without continuous CPU involvement.
DMA modes include burst, cycle stealing and transparent mode.
SRAM is fast, while DRAM provides higher density.
Flash and EEPROM are non-volatile memories.
A system bus includes address, data and control lines.
Bus arbitration selects one master among multiple requesters.
Synchronous buses use a clock, while asynchronous buses use handshaking.
Important RGPV Exam Questions
Long Answer Questions
Explain the memory hierarchy of an embedded system with a neat diagram.
Define cache memory and explain cache hit, cache miss and average access time.
Explain direct, associative and set-associative cache mapping.
Explain cache replacement and write policies.
What is virtual memory? Explain its advantages and limitations in real-time systems.
Explain paging and page-table organization.
Draw and explain Memory Management Unit architecture.
Explain virtual-to-physical address translation.
What is a TLB? Explain TLB hit and TLB miss.
Explain DMA architecture and its working.
Explain burst, cycle-stealing and transparent DMA modes.
Compare SRAM and DRAM.
Explain ROM, PROM, EPROM and EEPROM.
Compare Flash memory and EEPROM.
Explain memory interfacing and address decoding.
Explain system-bus architecture.
Explain different bus-arbitration techniques.
Differentiate synchronous and asynchronous buses.
Short Answer Questions
Define locality of reference.
What is cache-hit ratio?
What is a dirty bit?
Define a page fault.
What is a TLB?
State two functions of an MMU.
What is cycle stealing?
Differentiate SRAM and DRAM.
What is chip-select signal?
Define bus arbitration.
Exam Tip: Practice diagrams of memory hierarchy, cache organization, paging, MMU, address translation, DMA controller, memory interfacing and bus arbitration.
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Memory Diagrams
Exam-ready architecture diagrams coming soon.
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PYQ Analysis
Repeated Unit 4 questions coming soon.
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Frequently Asked Questions
Cache stores frequently used instructions and data close to the processor so that average memory-access time is reduced.
No. Cache mainly improves speed, while virtual memory provides address translation, protection and a logical address space.
The MMU translates virtual addresses into physical addresses and checks memory-access permissions.
DMA transfers data directly between memory and peripherals, so the CPU does not have to execute instructions for every transferred item.
SRAM is faster and does not need refresh, while DRAM is denser and cheaper but requires periodic refresh.
It prevents multiple bus masters from using and driving a shared bus at the same time.